Session Xx: Special Purpose Accelerators Fam 20.4: a Dynamically Reconfigurable Interconnection Chip
نویسندگان
چکیده
DYNAMIC RECONFIGURATION OF INTERCONNECTION is important in today's multiprocessing computing systems. A reconfigurable network between processing elements is essential for systolic array, vector processing, or pipeline processing systems. This paper focuses on the development of a Link and INterconnection Chip (LINC), an interface chip optimized for dynamically reconfiguring the data flow and sequencing the processing elements (multipliers, memory, ALU) of a computing system. 'iVith the LINC chip: one can optimize the data flow and sequencing required to compute each algorithm executed in a system application. Key functions include data synchronization. computational resource scheduling and compensation for variable pipeline latency. In addition, the control memory must permit the down load of new execution sequences concurrent with normal operation.
منابع مشابه
The Microprocessor is no more General Purpose : why Future Reconfigurable Platforms will win
The paper is a plaidoyer for a radical methodological change in R&D of dynamically reconfigurable circuits. The paper illustrates, that the current main stream approach based on placement and routing is not very likely to obtain the area-efficiency and throughput needed to cope with the emerging crisis cost of future silicon technology generations. The proposed changes include both: architectur...
متن کاملIntroduction to the Future of Reconfigurable Computing and Processor Architectures
As technology scales up, the design productivity slows down and new approaches must be sought after to reach the design productivity (or bridge the gap) that is nowadays common for general-purpose processor design. New tools, technologies, languages, operating systems, and design approaches are likely to be needed. Nowadays, extra transistors are utilized for acceleration purposes (next to prot...
متن کاملHybrid Hardware/Software Co-execution using Continuations
Upcoming computer architectures will include additional computational elements besides one or more general purpose processors. For instance, IBM, Sony and Toshiba have developed the Cell processor, composed of a PowerPC processor and up to eight Synergistic Processing Elements (SPEs). Xilinx offers the Virtex-II Pro, a chip which includes two PowerPC cores surrounded by a Field Programmable Gat...
متن کاملFolded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array
Fat H-Tree is a novel on-chip network topology for a dynamic reconfigurable processor array. It includes both fat tree and torus structure, and suitable to map tasks in a stream processing. For on-chip implementation, folding layout is also proposed. Evaluation results show that Fat H-Tree reduces the distance of H-Tree from 13% to 55%, and stretches the throughput almost three times.
متن کاملA High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator
In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by using a novel dynamically reconfigurable accelerator. Conventional microprocessors consume a large amount of power for memory access, in registers, and for the control of the processor...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2001